1. Field of the Invention
The present invention relates to microprocessor cores. In particular, the invention relates to reducing power consumption in a microprocessor core by not reloading operands into the core""s data-path if they do not change.
2. Description of the Related Art
In a microprocessor, the core performs the function of processing data into desired results. FIG. 1 illustrates an exemplary core 100 in a reduced instruction set computer (RISC) architecture, for example, the CR16A Compact RISC architecture from National Semiconductor Corp., Santa Clara, Calif. Core 100 includes data bus 110, operand storage circuits 120, control unit 130, load command lines 140, operating circuits 150, selection circuit 160, select signal lines 170, data path input lines 180, and result signal lines 190.
Data bus 110 transmits data to be processed by core 100. Operand storage circuits 120 store operands transmitted by the bus for processing by operating circuits 150. Control unit 130 generates load commands on load command lines 140 that instruct operand storage circuits 120 to load the operands from data bus 110. During a clock cycle, data bus 110 transmits a first operand and a second operand, and control unit 130 instructs operand storage circuit 121 to store the first operand and operand storage circuit 122 to store the second operand.
The first and second operands are provided to operating circuits 150 on data path input lines 180. General types of operating circuits include an arithmetic and logic unit circuit (ALU) 152, a multiplier circuit 154, and a third operating circuit 156, among other circuits. Result signal lines 190 transmit the processing results to selection circuit 160. Control circuit 130 sends a select signal on select signal lines 170 to select a selected result from operating circuits 150. The selected result is transmitted on result signal line 199.
A concern is the power consumed by the core. This is significant for portable devices. One reference has set forth the relationship as follows:
P=CV2F
where P is the power consumed by the core, C is the capacitance of the core logic elements, V is the voltage supplied to the core, and F is the frequency of the core operating circuits. The above equation has suggested a number of solutions to the power consumption problem.
One solution is to reduce the voltage. This has the benefit of quadratically reducing the power consumption. Consequently, a number of portable microprocessors today operate at 3.3 volts, whereas non-portable microprocessors generally operate at 5 volts.
Another solution is to shut down completely the microprocessor when it is not needed, and to restart it when necessary.
Still another solution is to lower the clock frequency of the microprocessor. A microprocessor is not fully occupied with data processing all the time, and during times of light processing loads the frequency can be reduced with no perceived reduction in throughput.
However, even by implementing all the above solutions, there is still a need to further reduce the power consumed by a microprocessor.
The present invention addresses these and other problems of the prior art by providing an apparatus for and method of reducing the power consumed by a microprocessor core. The apparatus and method reduce power by not loading operands into the core""s data path when they are already there.
According to one embodiment, an apparatus according to the present invention has a core circuit for implementing a microprocessor core, the core circuit including at least one data bus, a plurality of operand storage circuits, at least one operating circuit, and a control circuit. The data buses are configured to transmit a plurality of operands. The operand storage circuits are connected to the data buses, are configured to receive a plurality of load commands and in accordance therewith to load the operands, and are configured to output the operands. The operating circuits are connected to the operand storage circuits and are configured to receive the operands and in accordance therewith to generate a result signal. The control circuit is connected to the operand storage circuits and the operating circuits, and is configured to selectively generate the load commands to load selected operands. Power is conserved by loading only the selected operands.
According to another embodiment, a method according to the present invention reduces the power consumed by a microprocessor core. The method includes the steps of storing a plurality of current operands, comparing a next processing command with one or more stored processing commands, selectively replacing one or more current operands with one or more next operands, as indicated in the step of comparing. The method further includes the step of processing, according to the next processing command, the next operands and the current operands remaining after the step of selectively replacing, to generate a result signal. Power is conserved by replacing only the selected operands.